Features CoE

Depending on the main PDO/optional PDOs, further settings can be selected in the CoE list (CAN over EtherCAT).

The following CoE settings are possible from object 0x8010 and are shown below in their default settings:

Fig.45: “CoE online” tab

The parameters are described on page Object description and parameterization.

Frequency

• The time window for the frequency calculation and the resolution can be parameterized in CoE objects 0x8010:11, 0x8010:13, 0x8010:15, 0x8010:17.
• The positive edges of track A are counted within the specified timeframe and the next edge including the time up to it are counted. The waiting time can be set in CoE object 0x8010:17 “Frequency Wait Time” (unit: ms). The default value is 1.6 sec. This is also the maximum value.
• The time window is 10 ms (default), min. 1 µs. With the default setting it is possible to measure frequencies up to approx. 800 kHz. At higher frequencies a smaller value must be selected for the timeframe.
• The time is measured with a resolution of 100 ns.
• This calculation is carried out in the slave without reference to the distributed clocks system. It is therefore independent of the DC mode.
• No frequency measurement is possible if the counter is blocked by the gate. In this case the period can be measured regardless.
• If an encoder signal only is only present at input A/A and the frequency/period is to be measured, the terminal must be set to “Up/Down Counter” in CoE 0x8010:03.
• A C or external reset restarts the frequency measurement. The last frequency value remains unchanged until a new frequency value is determined.

Frequency measurement

• Basic unit 1 µs: all window sizes

Measurement sequence

• The measurement starts with a positive edge at track A. The current counter value and time (resolution: 100 ns) are stored.
• After the measuring window time has elapsed (index 0x8010:11), the system waits for the following rising edge at track A or a maximum of 1.6  sec or the time from 0x8010:17
• The frequency is calculated from the edge difference and the actual elapsed time.

Fig.46: Frequency measurement principle in enhanced operation mode

Period calculation

• This calculation is carried out in the slave without reference to the distributed clocks system. It is therefore independent of the DC mode.
• In each cycle the interval between two positive edges of input A is counted with a resolution of 100 ns.
• If no edge change occurs for approx. 1.6 s, any period specification is cancelled.

Frequency and period measurement From the explanatory notes above it is apparent that the frequency measurement can measure the current axis status (velocity) significantly more accurately than the period measurement. Frequency measurement is therefore preferable, if possible.

Latch

• Activating the latch C input (C) and latching the counter value
• Upon the first external latch pulse (positive edge at input C) after setting the bit in the output process data “Enable latch C” (index 0x7010:01) = TRUE, the counter value is saved (this takes precedence over the process data “Enable latch extern on postitive/negative edge” (index 0x7010:02/0x7010:04)).
  Subsequent pulses at the other inputs have no effect on the latch value in the input process data “Latch value” (index 0x6010:12) when the bit is set.

“Latch C valid” bit Only when the value in the input process data “Latch C valid” (index 0x6010:01) is FALSE can a new counter value be written to the latch input.

• Activating the external latch input (“gate/latch”) and latching the counter value
• If the bit in the process data “Enable latch extern on positive edge” = TRUE (index 0x7010:02), the counter value is stored in the latch input in the input process data “Latch value” (index 0x6010:12) upon the first external latch pulse with a rising edge. The following pulses have no effect on the latch value in the input process data “Latch value” (index 0x6010:12).
• If the bit in the process data “Enable latch extern on negative edge” = TRUE (index 0x7010:04), the counter value is stored in the latch input in the input process date “Latch value” (index 0x6010:12) upon the first external latch pulse with a falling edge. The following pulses have no effect on the latch value in the input process data “Latch value” (index 0x6010:12).

“Latch extern valid” bit Only when the value in the input process data “Latch external valid” (index 0x6010:02) is FALSE can a new counter value be written to the latch input.

Reset

• Counter reset (index 0x8010:01, 0x8010:02, 0x8010:10): For a counter reset via input C set the bit in index 0x8010:01, for a reset via the external latch input set the bit in index 0x8010:02.
• The functions “Enable C reset” (0x8010:01) and “Enable extern reset” (0x8010:02) cannot be activated simultaneously.
• Note for “Extern reset polarity”, index 0x8010:10: The edge for setting the counter to zero can be selected via index 0x8010:10.
  Bit not set: counter is set to zero with falling edge.
  Bit set: counter is set to zero with rising edge.

Up/down counter

• The mode (encoder or up/down counter) is set via the CoE objects (profile-specific objects, tab CoE - Online, index 0x8010:03 “Enable up/down counter”). Click on the corresponding row of the index to be parameterized, enter 1 in the SetValue dialog and confirm with OK.
• Set the gate polarity accordingly via index 0x8010:04.
• An additional option for reversing the rotation direction is available by setting the bit in index 0x8010:0E.

Over-/underflow 

• When combined with an enabled reset function (C/external), the over/underflow check is disabled.
• The bit in the input process data “Counter underflow” (index 0x6010:04) is set when an underflow …00 →…FF occurs. It is reset if 2/3 of the counter range is underrun.
• The bit in the input process data “Counter overflow” (index  0x6010:05) is set when an overflow from FF… to 00… occurs. It is reset if 1/3 of the counter range is exceeded.

Wire break detection “Open circuit detection”

• A separate wire break detection can be activated for each of the channels A, B, and C (index 0x8010:0B, 0x8010:0C, 0x8010:0D).
• Wire break detection is activated for channels A and B by default.
• A differential voltage of typ. -1.5 V > Vid > +1.5 V is detected as a wire break.
• A detected wire break is indicated by setting the bit in the process data “Open circuit” (Index 0x6010:07) to TRUE. A wire break is also indicated separately in indices 0xA010:01 (track A), 0xA010:02 (track B), and 0xA010:03 (track C).
• The bit in the input process data “TxPDO State” also becomes TRUE when a wire break is detected, since the data must be assumed to be invalid.

Micro-increments

• Works with and without distributed clocks, but is only meaningful in conjunction with one of the DC modes
• By setting the counter value only the integer component can be modified.
• The principle:

Fig.47: Frequency measurement principle in enhanced operation mode

The highly constant query cycles (accuracy: 100 ns) of the distributed clocks systems enable the terminal to interpolate axis positions between the counted encoder increments from a certain speed. The interpolation resolution is 8 bit, corresponding to 256 values. A standard encoder with 1,024 bars with 4-fold evaluation and micro-increments thus becomes a high-resolution axis encoder with 4096 * 256 = 1,048,576 bars.
Underrunning of the minimum velocity is indicated by the object 0x6010:08 (extrapolation stall) in the process data.