Gate input
An external input, “Gate”, for 24 V DC signals with a minimum pulse duration of tON > 1 µs is available and can be used as follows:
- Lock counter value:
Lock the counter value via a positive or negative edge (index 0x80n0:04 “Gate polarity” = “Enable pos/neg. gate”) - Save counter value:
Save the counter value, in separate process data, via a positive or negative edge (output process data “Enable latch extern 2 on positive/negative edge” (0x70n0:0C/0D))
Lock counter value via a positive/negative edge at the gate input (Enable pos./neg. gate)
- The level at the gate input at which the counter value is locked during runtime can be specified via index 0x80n0:04 “Gate polarity”.
- 0: Disable gate
The “Gate” input is disabled. It can still be used as “Latch extern 2” input. - 1: Enable pos. gate
The counter value is locked with a HIGH level at the “Gate” input. - 2: Enable neg. gate
The counter value is locked with LOW level at the “Gate” input. - The current level at the “Gate” input is displayed via process data “Status of input gate” (0x60n0:0C).
Save the counter value via a positive/negative edge on the “Gate” input (Enable latch extern 2 on positive/negative edge)
The “Gate” input may be used as a second latch input (Latch extern 2). To do this, the gate should be disabled.
![]() | Deactivation of the gate Set the “Gate polarity” bit (index 0x80n0:04) to “0 – Disable gate” in order to be able to use the “Latch extern 2” input without locking the counter value after the latch event. |
- The counter value at the “Latch extern 2” input can be saved via:
- Process data “Enable latch extern 2 on positive edge” (0x70n0:0C) = TRUE
At the first external pulse with positive edge at the “Gate” input, the current counter value is stored in the process data “Latch value 2” (0x60n0:22). - Process data “Enable latch extern 2 on negative edge“ (0x70n0:0D) = TRUE
At the first external pulse with negative edge at the “Gate” input, the current counter value is stored in the process data “Latch value 2” (0x60n0:22). - Simultaneous activation of the bits in the process data “Enable latch extern 2 on positive edge” (0x70n0:0C) and “Enable latch extern 2 on negative edge” (0x70n0:0D)
When the first pulse is received at the “Gate” input–regardless of the polarity of the edge–the current counter value is stored in the process data “Latch value 2” (0x60n0:22). - Specification whether it is necessary to reactivate the command to save the counter value via:
- “Enable continuous latch extern 2” Index 0x80n0:23 = FALSE
The following pulses at the “Gate” input have no effect on the latch value in the process data “Latch value 2” (0x60n0:22) when the bit in the process data “Enable latch extern 2 on positive edge” (0x70n0:0C) or “Enable latch extern 2 on negative edge” (0x70n0:0D) is set.
Only when the bit in the process data “Latch extern 2 valid” (0x60n2:12) is FALSE can a new counter value be written to the “Gate” input in the process data “Latch value 2” (0x60n0:22). - “Enable continuous latch extern 2” Index 0x80n0:23 = TRUE
The counter value is written to the process data field “Latch value 2” (0x60n2:22) each time a configured edge is detected at the “Gate” input.
There is no need to reactivate the bits in the process data “Enable latch extern 2 on positive edge” (0x70n0:0C) or “Enable latch extern 2 on negative edge” (0x70n0:0D). - The status of the input “Gate” can be recorded via the process data “Status of input gate” (0x60n0:0C).
- Saving of the counter value in the process data “Latch value 2” (0x60n0:22) is confirmed by the bit in the process data “Latch extern 2 valid” (0x60n2:12).
![]() | Simultaneous use of Gate and Latch extern 2 When using the index 0x80n0:04 “Gate polarity” (1 = “Enable pos. gate”) and simultaneous activation of the output process data “Enable latch extern 2 on positive edge” (0x70n0:0C), a positive edge on the “Gate” input first stores the current counter value in the input process data “Latch value 2” (0x60n0:22). After that, the counter value is locked. The same applies to the use of index 0x80n0:04 “Gate polarity” (2 = “Enable neg. gate”) and the simultaneous activation of the output process data “Enable latch extern 2 on negative edge” (0x70n0:0D) when a negative edge occurs at the “Gate” input. |
![]() | Multiple activation of the latch function If several commands are activated simultaneously to save the counter value in the “Latch value” process data (0x60n0:12), only the command that is set first is accepted by the terminal.
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