EJ8xxx - Signal-Distribution-Board for standard EtherCAT plug-in modules

Structure of the PCB layers

 

Requirements of the PCB

A multilayer PCB with at least four Layers is recommended for EJ-Backplane, in order to allow complete covering of the differential pairs with copper (GND net) from both sides of the PCB.

 
Note
Avoid damage of backplane and components!
Short circuit condition has to be taken into account for cross section configuration.

The snap in mechanism of the EJ-Modules is designed for a PCB thickness of 1.6 mm ±10%.

 
Requirements of the pcb (min. 4 layers, max. 1.6 mm thickness)
 

The following figures show an example for a PCB with 4 layers with the routing in the individual layers.

 
Note
Note on routing
Read the notes on routing in chapter Module placement, Design of power supply and Routing guildelines!
If necessary, read the routing instructions in chapter pinout in the documentations of the modules used.
 
 

Top layer

 
Top layer
Keep 0 V Us power supply as close as possible to the coupler in order to avoid unnecessary antennas.
0 V Us/Up and 24 V Us/Up should be routed at different layers.
The SGND shield ground pins may be connected and routed on the top layer.
SGND connection to the control cabinet shall be implemented as metal bolts building a direct connection between back plane and control cabinet. The copper rings around the holes are connected to SGND.
A cable based SGND connection to the control cabinet shall be avoided.
It is recommended to route the signals SGND, 0 V Us/Up and 24 V Us/Up as an area.
 
 

Inner layer 1

 
Inner layer1
The E-bus traces have to be routed in inner layers, in order to allow complete covering of the differential pairs with copper (GND net) from both sides of the PCB.
On the E-bus TX and RX routing layer free space between the signals shall be filled with copper connected to GND.
Impedance and Routing
The differential impedance of the LVDS traces shall be 100Ω.
Width and spacing of the differential signal are depending on the concrete layer stack up and have to be calculated individually.
The differential signals should be routed as edge coupled traces.
The distance between the differential pairs should be three times larger than their inner distance (see Figure above).
Differential pairs should be routed without Vias (vertical interconnect access), in order to avoid impedance jumps.
Maximum values for uncoupled trace and overall trace length can be found in the specification for LVDS signals ANSI/TIA/EIA-644 "Electrical Characteristics of Low Voltage Differential Signaling (LVDS)".
It is recommended to route SGND as an area.
 
 

Inner layer 2

Inner layer 2
I/O Signals should be routed in the inner layers, as Covering of signal lines from both sides with SGND can improve insensibility against EMC disturbances.
Additionally the space between signal lines and signal groups should be filled with copper on SGND potential.
It is recommended to route SGND as an area.
 
 

Bottom layer

Bottom Layer
Keep 24 V Us power supply as close as possible to the EJ1100 coupler in order to avoid unnecessary antennas.
0 V Us/Up and 24 V Us/Up should be routed at different layers.
24 V Us should be galvanically separated from 24 V Up.
It is recommended to route the signals SGND, 0 V Us/Up and 24 V Us/Up as an area.