Process data mode
Control byte 1 in process data mode
Control byte 1 (CB1) is located in the output image, and is transmitted from the controller to the terminal.
Bit | CB1.7 | CB1.6 | CB1.5 | CB1.4 | CB1.3 | CB1.2 | CB1.1 | CB1.0 |
Name | RegAccess | - | RS_CNT_LAT | EnLatchFall | EnLatchRise | SetCnt | ReadLatch | EnLatchC |
Key
Bit | Name | Description | |
---|---|---|---|
CB1.7 | RegAccess | 0bin | Register communication off (process data mode) |
CB1.6 | - | reserved | |
CB1.5 | RS_CNT_LAT* | 1bin | The counter is set to zero by an active edge at the latch input. Bits CB1.4, CB1.3 and CB1.0 specify which edge of the latch signal is active. |
CB1.4 | EnLatchFall* | 1bin | The falling edge of the latch input is active. The counter value is stored in the latch register at the first external latch impulse after the EnLatchFall bit becomes true. The subsequent pulses do not have any effect on the latch register. |
CB1.3 | EnLatchRise* | 1bin | The rising edge of the latch input is active. The counter value is stored in the latch register on the first external latch pulse after the EnLatchRise bit becomes true (this has priority over EnLatchFall). The subsequent pulses do not have any effect on the latch register. |
CB1.2 | SetCnt | A rising edge at SetCnt will set the counter to the 32 bit value that is written by the controller into the process output data. | |
CB1.1 | ReadLatch | 0bin | The current value of the 32 bit counter is mapped to the process input data. |
1bin | The 32 bit value stored in the latch counter is mapped to the process input data. | ||
CB1.0 | EnLatchC* | 1bin | The rising edge of the zero input (input C) is active. The counter value is stored in the latch register at the first external latch impulse after the EnLatchC bit becomes true. The subsequent pulses do not have any effect on the latch register. (see note below) |
*) Does not apply to KL5152-0000 (KL5151-0050), since the latch input and zero input are not available in this case. Always set bits CB1.5, CB1.4, CB1.3 and CB1.0 of the KL5152-0000 (KL5151-0050) to 0bin!
![]() | EnLatchC or EnLatchRise and EnLatchFall? If bit CB1.0 (EnLatchC) is set, bit CB1.3 (EnLatchRise) and bit CB1.4 (EnLatchFall) must not be set, otherwise you cannot know which event has caused a counter value to be stored in the latch. |
Status byte 1 in process data mode
The status byte 1 (SB1) is located in the input image, and is transmitted from terminal to the controller.
Bit | SB1.7 | SB1.6 | SB1.5 | SB1.4 | SB1.3 | SB1.2 | SB1.1 | SB1.0 |
Name | RegAccess | - | - | StGate | StLatchC | SetCnt | ReadLatch | ValLatchC |
Key
Bit | Name | Description | |
---|---|---|---|
SB1.7 | RegAccess | 0bin | Acknowledgement for process data mode |
SB1.6 | - | reserved | |
SB1.5 | - | reserved | |
SB1.4 | StGate | KL5151-0000: Status of the external gate/latch input | |
KL5152-0000 (KL5151-0050): reserved | |||
SB1.3 | StLatchC | KL5151-0000: Status of the zero input (input C) | |
KL5152-0000 (KL5151-0050): reserved | |||
SB1.2 | SetCnt | Acknowledgement that the data for setting the counter has been adopted by the terminal. | |
SB1.1 | ReadLatch | 0bin | The current value of the 32 bit counter has been mapped to the process data. |
1bin | The 32 bit value stored in the latch counter has been mapped to the process data. | ||
SB1.0 | ValLatchC* | 1bin | A zero-point latch has occurred: a rising edge at the zero input (input C) has caused the current counter value to be stored in the latch register as a reference mark.
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*) Does not apply to KL5152-0000 (KL5151-0050), since the latch input and zero input are not available in this case.