DC settings

Distributed Clocks (DC)

EtherCAT and Distributed Clocks A basic introduction into EtherCAT and distributed clocks is available for download from the Beckhoff website: the “Distributed clocks system description”.

The incremental encoder terminals support the distributed clocks function (EL5101: from Hardware 09 / Firmware 14; EL5151 from Hardware 01 / Firmware 05). In order for the EL51xx to be able to make the current counter value available in the designated process data in time before the arrival of the querying EtherCAT datagram, a suitable signal must be generated cyclically within the terminal. This signal can be triggered in the EL51xx through two events: the SyncManager (SM) and the distributed clock (DC). Under operation mode selection the following options are available (see Fig. 1)

• FreeRun/SM-Synchron
  The SynManager event occurs when an EtherCAT frame successfully exchanges process data with the EL51xx. Frame-triggered, the current counter value is thus cyclically determined, but with the low temporal jitter of the Ethernet frame. In this mode an Ethernet frame triggers the process data provision for the next retrieving frame. This generally only occurs after 1x cycle time.
• DC Synchronous
  In DC mode, a counter reading is triggered by the integrated DC unit with a constant cycle, usually in synchrony with the bus cycle, although with a constant shift (phase, shift time, offset). Sampling is significantly more uniform (synchronization accuracy: 100 ns), which means a higher-level control algorithm can be supplied with higher-quality position data, for example. In the EL51xx the trigger is the SYNC0 signal, which is set like an output component in “DC-synchron” mode. See Distributed Clocks system description.
  The DC modes enable the start time of the process data provision to be offset by an offset value (shift value). This offset value can only by set on EtherCAT startup and can then no longer be changed during the uptime. Based on the general distributed clocks SYNC function model, the terminal-specific SYNC signal can either occur before or after the expect frame pass-through time: For input terminals the SYNC signal is generated before the frame, in order to make current input data available for forwarding. For output terminals the SYNC signal is set to a time after the frame has passed through, so that the just supplied data are output immediately. Since only one of the two modes is possible, the user can set the optimum mode for his application.
  "DC Synchronous" corresponds to the output module configuration. The local SYNC event is triggered shortly after the EtherCAT frame has passed.
• DC-Synchron (input based)
  In the “DC-Synchronous (input based)” mode this EL51xx is assigned to the group of input modules and the shift time (see Fig. Advanced Distributed Clock (DC) settings, EL51xx terminal) is calculated accordingly.

When “DC-Synchronous” operating mode is activated, TwinCAT selects settings that ensure reliable operation of the EL51xx and the acquisition of current position data. This means that determination of the current counter value is started by the SYNC0 signal at highly constant intervals and in the operating mode “DC-Synchronous (input based)” in good time – i.e. with an adequate safety buffer – before the retrieving EtherCAT datagram.

Duration of the process data provision in the EL51x1 The EL5101 (from Hardware 09 / Firmware 14) or the EL5151 (from Hardware 01/ Firmware 05) requires approx. 80 µs after the SYNC event to determine the position data and provide them for retrieval. This value depends on the configuration and parameterization. The actual current duration can be read using the internal DC functions, see CoE setting in 1C32:08 and the result in 1C32:05.

If necessary, the SYNC0 signal can be shifted along the time axis to the right/later or left/earlier in associated dialogs by specifying a “User defined Shift Time”, see Fig. Advanced Distributed Clock (DC) settings, EL51xx terminal.

• A right-shift (positive shift value) will delay the counter value query, which means the position value becomes more current from the PLC perspective. However, this increases the risk that the position determination may not be finished in time before the arrival of EtherCAT frame, so that no current position value is available in this cycle.
• A left-shift (negative shift value) means the counter value will be queried earlier, resulting in older position values, with an associated increase in the safety buffer before the arrival of the EtherCAT datagram. This setting may be useful in systems with high real-time jitter, if no Industrial PCs from Beckhoff are used for control purposes, for example.

Default setting

The cyclic read of the inputs is triggered by the SYNC0 pulse (interrupt) from the DC in the EL51xx. The EtherCAT master sets the Sync Unit Cycle time value to the PLC cycle time and therefore the EtherCAT cycle time as standard. See Fig. Advanced Distributed Clock (DC) settings, EL51xx terminal: 4000µs = 4 ms, as TwinCAT is in configuration mode.

EL51xx DC settings

• SYNC0
  Sync unit cycle: a multiple of the bus cycle time. The counter value is periodically determined at this interval (in µs).
• User-defined
  Arbitrary number up to 2³² ns ≈ 4.3 secs. Decimal point values are possible.
• Shift Time
  The Shift Time can be used to shift the SYNC0 pulse for this EL51xx relative to other terminals and the global SYNC pulse in nanosecond steps. If the data of several EL51xx terminals are to be read simultaneously, the same value must be entered here.
  
• Based on input reference
  If this option is activated an additional Input Shift is added to the configurable terminal-specific SYNC0 shift (user-defined). This value is calculated and made available by the EtherCAT master (SysMan/EtherCAT device/EtherCAT tab/Advanced Settings/Distributed Clocks/Input Shift Time/, see Fig. EtherCAT Master, EtherCAT tab, Advanced Settings + EtherCAT Master, Advanced Settings, Distributed Clock). In this way all input terminals in the system (EL1xxx, EL3xxx and appropriately set ELxxxx such as the EL51xx) read their inputs as close as possible to the time of the EtherCAT frame that will fetch them, thereby supplying the most recent possible input data to the controller. In input-based mode this value is taken into account automatically.
  
• Enable SYNC0
  Automatically activated in DC Synchronous operating mode.
• SYNC1
  Additional SYNC pulse, derived from SYNC0 or from the DC itself. Not required by the EL51xx.

DC settings for EtherCAT master

Higher-level distributed clock parameters can be modified under advanced settings for the EtherCAT master. Refer also to the basic introduction to the topic of EtherCAT and Distributed Clocks; download: the “Distributed clocks system description”.