Basic function principles
Delivery state
It is not necessary to make any particular settings when operation of the EL2262 is first started. The EL2262 operates as a normal 2-channel digital output terminal.
 | XML Device Description If the XML description of the EL2262 is not available in your system you can download the latest XML file from the download area of the Beckhoff website (http://www.beckhoff.de/german/default.htm?download/elconfg.htm) and install it according to the installation instructions. |
Functioning
The EL2262 is a digital output terminal with two channels. In the EL2262 the ESC (EtherCAT slave controller) handles the data communication to the EtherCAT fieldbus and supports the distributed clock functionality. The ESC can thus cyclically switch the outputs of the EL2262 at highly precise, equidistant intervals. If the EtherCAT frame transfers the data to the EL2262, a complete process data block can be processed. The temporal resolution of the outputs can take place much faster than the fieldbus cycle and is therefore called oversampling.
Distributed Clock
Oversampling requires a clock generator in the terminal that triggers the individual output patterns. The local clock in the terminal, referred to as distributed clock, is used for this purpose.
The distributed clock represents a local clock in the ESC with the following characteristics:
Unit 1 ns
Zero point 1.1.2000 00:00
Size 64 bit (sufficient for the next 584 years); however, some EtherCAT slaves only offer 32-bit support, i.e. the variable overflows after approx. 4.2 seconds
The EtherCAT master automatically synchronizes the local clock with the master clock in the EtherCAT bus with a precision of < 100 ns.
The EL2262 only offers 32-bit support.
| EtherCAT and Distributed Clocks A basic introduction into EtherCAT and distributed clocks is available for download from the Beckhoff website: the "Distributed Clocks system description". |
Example:
The fieldbus/EtherCAT master is operated with a cycle time of 1 ms to match the higher-level PLC cycle time of 1 ms, for example. This means that every 1 ms an EtherCAT frame is sent to the EL2262 for transferring the process data. The local ESC clock therefore triggers an interrupt in the terminal every 1 ms (1 kHz), in order to read the process data provided by the EtherCAT frame. This first interrupt is called SYNC1.
The EL2262 is set in the TwinCAT System Manager to an oversampling n of 1000; see fig. Selection dialog for EL2262 oversampling factors in the TwinCAT System Manager, "DC" tab. This causes the ESC to generate a second interrupt in the terminal with an n-times higher frequency, in this case 1 MHz or 1 µs period. This interrupt is called SYNC0. With each SYNC0 signal a new bit is read from the current data set per channel and output to the power step.
Generation of the SYNC0 pulse from the local synchronized clock within the distributed clock network ensures that the output values are output at highly equidistant intervals with the period of the SYNC1 pulse.
The oversampling factor for the EL2262 can be set to predefined values between 1 and 1000.
Please note that the EL2262 process image characteristics change depending on the oversampling factor, see Process data description.
| Oversampling factor Regarding the calculation of SYNC0 from the SYNC1 pulse based on manual specification of an oversampling factor, please note that for SYNC0 only integer values are calculated at nanosecond intervals. Example: 187,500 µs is permitted, 333.3̅ µs is not. |
The EL2262 supports a max. output frequency of 500 kHz or 1 Msample/sec and thus achieves a graduation of the switching flanks of as little as 1 µs. For electrodynamic reasons a max. output frequency of 100 kHz is recommended up to and including hardware version 05.