Explanation of the output behavior in case of error (Watchdog, CycleCounter)

Behavior in case of error - Watchdog and CycleCounter

This output terminal depends on regular supply of cycle updated data from the controller. If this is not the case, two phases are to be distinguished and the following tools take effect

• Short absence (one cycle and more) → CycleCounter monitoring
  In CycleCounter monitoring, the device wants to be assigned cyclically incremented values (+1) from the controller in the CycleCounter process data variables. Thus, it can determine whether a frame repetition or a LostFrame has occurred based on the consecutive values. If CycleCounter monitoring is not activated, the firmware is unable to detect the non-arrival of data and repeats the data of the last sample until the watchdog has run out.
• Diagnosis: If no increment +1 is detected by the device, at least the internal register 030D_hex "PDI-Error" counts up by 1. A counter overflow 255 → 0 is not interpreted as an error. If the counter increment is greater than 1 once and subsequently 1 again, only one PDI error is output, since all the counter values after the event have an increment of 1. This register can be read out acyclically, e.g. by the PLC, see "Explanations on CycleCounter monitoring".
• Output behavior: Furthermore, in this case the firmware continues to use the output according to the ESC register setting:
• for channel 1: Register 0x0F00
  Bit 0 = TRUE → Parameterization is activated
  Bit 1 to 3: Default value for behavior at CycleCounterError, see below.
• for channel 2: Register 0x0F01
  Bit 0 = TRUE → Parameterization is activated
  Bit 1 to 3: Default value for behavior at CycleCounterError, see below.
• Note: The two byte registers 0x0F00 and 0x0F01 should be written simultaneously as 1 word access.
• Possible register values for the CycleCounter behavior are (names are taken from the demo program below):
  ZERO: "000": A logical zero "0" is output (default)
  ONE: "001": A logical one "1" is output
  HOLD: "010": The value of the last bit in the previous cycle is output
  CONTINUE: "011": A PDI error is output, but the data currently in the buffer is output. This can also be outdated data.
  ALT: "100": zero and one are output alternately
  OFF: "101" (EL2262 only): the output stage is switched to high-resistance. No signal level is driven.
  
  Figure from TC3 sample program
• Prolonged absence (watchdog time and longer) → SM-Watchdog
  The device has a parameterizable SM-Watchdog (SyncManager watchdog) as output terminal. In each successful EtherCAT cycle this is 'wound up' again or reset. If it is not used for a certain time (default: 100 ms), the outputs are set to a definable state. For the time-based parameterization of the SM watchdog, see here.
• The output behavior after the watchdog has been triggered is parameterized via the ESC registers as follows:
• For channel 1: Register 0x0F00
  Bit 0 = TRUE → Parameterization is activated
  Bit 4 to 6: Default value for watchdog behavior, see below.
• Channel 2: Register 0x0F01
  Bit 0 = TRUE → Parameterization is activated
  Bit 4 to 6: Default value for watchdog behavior, see below.
• The default behavior for watchdog monitoring is output=FALSE
• Note: the two byte registers 0x0F00 and 0x0F01 must be written as 1 word access at the same time The default values for the watchdog behavior are:
• Possible register values for the watchdog behavior are (names are taken from the demo program below):
  ZERO: " "000": A logical zero is output (default)
  ONE: "001": A logical one is output
  HOLD: "010": The value of the last bit in the previous cycle is output
  REP: "011": The data of the last cycle is output repeatedly
  ALT: "100": Zero and one are output alternately
  OFF: "101" (EL2262 only): The output stage is switched to high-resistance. No signal level is driven

Since CycleCounter and Watchdog behavior are controlled by the same register, the two registers are to be described completely in 1 operation, see sample program.

Using the ESC registers If settings are loaded into ESC registers (in this case 0x0F00, for example), they are retained until they are overwritten or until the system is de-energized. If the system was de-energized, the required values have to be re-loaded into the registers.

The following example about the terminal function in case of a communication interruption illustrates the resulting 3 phases.

• Invented signals (as specified by the PLC) are output on channel 1 and 2 of a EL2262 and observed with an oscilloscope.
• For demonstration purposes, channel 1 and 2 are parameterized differently
• The example also applies to the EL1262-0010 (outputs).

Note on the EL2262:

CycleCounter monitoring demonstration

In this further example the watchdog is set to 25 ms. By default, the last sample block is output repeatedly in phase 2 until phase 3:

Fig.198: Default output behavior if CycleCounter monitoring is deactivated

If CycleCounter monitoring is activated, the default is output = FALSE in phase 2.

Fig.199: Default output behavior if CycleCounter monitoring is activated

Now the CycleCounter special behavior "ALT" in phase 2 is parameterized for channel 1 and the Watchdog special behavior "REP" for channel 2: :

Fig.200: Parameterized output behavior (system-specific)