Basic function principles
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Delivery state
It is not necessary to make any particular settings when operation of the EL1262 is first started. The EL1262 operates as a normal 2-channel digital input terminal.
 | XML Device Description If the XML description of the EL1262 is not available in your system you can download the latest XML file from the download area of the Beckhoff website and install it according to the installation instructions. |
Distributed Clock
Distributed Clock Oversampling requires a clock generator in the terminal that triggers the individual data sampling events. The local clock in the terminal, referred to as distributed clock, is used for this purpose.
The distributed clock represents a local clock in the ESC with the following characteristics:
- Unit 1 ns
- Zero point 1.1.2000 00:00
- Size 64 bit (sufficient for the next 584 years); however, some EtherCAT slaves only offer 32-bit support, i.e. the variable overflows after approx. 4.2 seconds
- The EtherCAT master automatically synchronizes the local clock with the master clock in the EtherCAT bus with a precision of < 100 ns.
The EL1262 only offers 32-bit support.
| EtherCAT and Distributed Clocks A basic introduction into EtherCAT and distributed clocks is available for download from the Beckhoff website. |
Example:
The fieldbus/EtherCAT master is operated with a cycle time of 1 ms to match the higher-level PLC cycle time of 1 ms, for example. This means that every 1 ms an Ethernet frame is sent to collect the process data from the EL1262. The local terminal clock therefore triggers an interrupt in the ESC every 1 ms (1 kHz), in order to make the process data available in time for collection by the EtherCAT frame. This first interrupt is called SYNC1.
Let's assume the EL1262 is set to an oversampling rate n = 1000 in the TwinCAT System Manager. See selection dialog for EL1262 oversampling factors in the TwinCAT System Manager. This causes the ESC to generate a second interrupt in the terminal with an n-times higher frequency, in this case 1 MHz or 1 µs period. This interrupt is called SYNC0. With each SYNC0 signal the voltage is sampled as a digital value (0/1) and the corresponding values are sequentially stored in a buffer.
Generation of the SYNC0 pulse from the local synchronized clock within the distributed clock network ensures that the input values are sampled at highly equidistant intervals with the period of the SYNC1 pulse.
The maximum oversampling factor depends on the memory size of the used ESC. In the KKYY0200 version of the EL1262 it is n = 1000.
The values accumulated in the buffer are sent as a packet to the higher-level controller. With two channels and n = 1000, 2 x 1000 = 2000 bits = 250 bytes of process data are transferred during each EtherCAT cycle.
The oversampling factor for the EL1262 can be set to predefined values between 1 and 1000.
Please note that the EL1262 process image characteristics change depending on the oversampling factor, see Process data description.
| Oversampling factor Regarding the calculation of SYNC0 from the SYNC1 pulse based on manual specification of an oversampling factor, please note that for SYNC0 only integer values are calculated at nanosecond intervals. Example: 187,500 µs is permitted, 333.3 µs is not! Values other than those offered in the dialog are not possible. If implausible values are used, the terminal will reach the OP state, but its behavior will correspond to an oversampling factor of 1, and only the first bit will contain valid data. Example: For SYNC1/EtherCAT cycle = 1 ms oversampling factors such as 1, 2, 5 or 100 are permitted, but not 3. |
Input characteristics
The input characteristics of the EL1262 meet the requirements of EN61131-2:2003 Type 1.
The input circuit of the EL12xx is optimized for fast signal changes and for the fastest possible signal acquisition. The duration required by a signal change (a rising or falling edge) to propagate from the clamping point at the front of the terminal through to the logic of the central evaluation unit (ESC) is specified for the EL12xx series as Ton/Toff < 1 µs, for both rising (Ton) and falling edges (Toff). The low absolute magnitude of this propagation time means that the temperature drift of the propagation time is also very small.
It should be borne in mind that the input circuit does not include any filtering. It has been optimized for the fastest possible signal transmission from the input to the evaluation unit. Fast level changes or pulses in the µs range therefore reach the evaluation unit unfiltered or unattenuated. It may be necessary to use screened cables in order to eliminate interference from the surroundings.
The sensor/signal transducer must be able to generate sufficiently steep signal edges. The power supply unit used should have sufficient buffer reserves to ensure that the signal reaches the terminal with a sufficiently steep edge in spite of capacitive or inductive cable losses.
Start-up behavior
From the time the EtherCAT fieldbus starts up the EL1262 takes around 60 bus cycles until it delivers process data in OP state for the first time and continuously.
Process data
The EL1262 offers a range of process data for transfer. In the default state the terminal appears in the System Manager as shown in EL1262 default state.
- Chx Cycle Count
EL1262 cycle counter: during each cycle the EL1262 increments this 16-bit counter by 1. The counter can be used to check the EL1262 for lost frames or data repetitions. The cycle counters for both channels show the same value. - Chx Input 0
Depending on the selected oversampling factor the digital input values are listed here, from 1 bit to 125 bytes per channel. - Gap
This variable is only used as a placeholder and does not represent a usable process data - NextSync1Time
As mentioned above the SYNC1 interrupt triggers provision of the accumulated process data in the EL1262 in synchrony with the fieldbus. The time of the SYNC1 interrupt is the same as the first SYNC0 interrupt, which determines sampling of the inputs. The NextSync1Time value transferred by the EL1262 during an EtherCAT cycle is the start value for the next SYNC1 interrupt with a resolution of 32 bit (see Distributed Clocks). The NextSync1Time process data can be deactivated in the ProcessData tab. NextSync1Time can be used to specify the read time for each individual sample within the distributed clock accuracy.
| Chx Input presentation The Chx Input process data must cover a large range of values from 1 to 1000 bits. In order to maintain a clear display of the configuration tree and the task variable links, the Chx Input variables are shown either as bit or byte. Oversampling factor <= 100: individual bits are displayed. Oversampling factor > 100: bits are consolidated as bytes. The task receiving the EL1262 process data therefore has to offer bit or byte arrays as appropriate. |
Tips for operation
Distributed Clocks settings
In the EL1262 Distributed Clock options under Advanced Settings the time of the SYNC1 interrupt can be shifted forward slightly, see EL1262 Advanced Settings, Distributed Clock. By activating the "Based on Input Reference" checkbox the SYNC1 interrupt is shifted forward by a few µs. For further information please refer to the Distributed Clock system description.
Linking large variables
The option “Change Multi Link” can be used to link larger memory areas with continuous variables. Proceed as follows:
