Configuration data
Index 80n0 ENC Settings 0 Ch.n (for n=0 [channel 1], n=1 [channel 2])
Index (hex) | Name | Meaning | Data type | Flags | Default |
---|---|---|---|---|---|
80n0:0 | ENC Settings 0 Ch. (n+1) | Maximum subindex | UINT8 | RO | 0x23 (35dec) |
80n0:01 | Enable C reset | The counter is reset via the C input. | BOOLEAN | RW | 0x00 (0dec) |
80n0:02 | Enable extern reset | A counter reset is triggered via the external latch input (24 V) | BOOLEAN | RW | 0x00 (0dec) |
80n0:04 | Gate polarity | 0: Disable gate 1: Enable pos. gate (gate locks with HIGH signal level) 2: Enable neg. gate (gate locks with LOW signal level) | BIT2 | RW | 0x01 (1dec) |
80n0:06 | Evaluation mode | 0: 4-fold (four-fold evaluation) 1: 1-fold (single evaluation) 2: 2-fold (two-fold evaluation) | BIT2 | RW | 0x00 (0dec) |
80n0:08 | Disable filter | 0: Activates the input filter (inputs A, /A, B, /B, C, /C only) 1: Deactivates the input filter | BOOLEAN | RW | 0x01 (1dec) |
80n0:0A | Enable micro increments | If activated, the module interpolates micro-increments between the integral encoder increments in DC mode. The lower 8 bits of the counter value are used in each case for the display. A 32-bit counter thus becomes a 24+8-bit counter, a 16-bit counter becomes an 8+8-bit counter. | BOOLEAN | RW | 0x00 (0dec) |
80n0:0B | Error detection A | A broken wire or short circuit on track A is indicated in index 0x60n0:07 and as process data. Diagnostics is only possible, if the associated input is wired differentially. | BOOLEAN | RW | 0x01 (1dec) |
80n0:0C | Error detection B | A broken wire or short circuit on track B is indicated in index 0x60n0:07 and as process data. Diagnostics is only possible, if the associated input is wired differentially. | BOOLEAN | RW | 0x01 (1dec) |
80n0:0D | Error detection C | A broken wire or short circuit on track C is indicated in index 0x6000:07 and as process data. Diagnostics is only possible, if the associated input is wired differentially. | BOOLEAN | RW | 0x00 (0dec) |
80n0:0E | Reversion of rotation | Activates reversion of rotation | BOOLEAN | RW | 0x00 (0dec) |
80n0:10 | Extern reset polarity | 0: Fall (the counter is set to zero with a falling edge) 1: Rise (the counter is set to zero with a rising edge) | BIT1 | RW | 0x01 (1dec) |
80n0:11 | Frequency window | This is the minimum time over which the frequency is determined; | UINT16 | RW | 0x2710 (10000dec) |
80n0:13 | Frequency scaling | Scaling of the frequency measurement (must be divided by this value to obtain the unit in Hz): 100: "0.01 Hz" (default) 1: "1 Hz" | UINT32 | RW | 0x00000064 (100dec) |
80n0:14 | Period scaling | Resolution of the period value in the process data: 10: "10 ns" Period value is a multiple of 10 ns 100: "100 ns" Period value is a multiple of 100 ns 500: "500 ns" Period value is a multiple of 500 ns | UINT32 | RW | 0x0000000A (10dec) |
Index (hex) | Name | Meaning | Data type | Flags | Default |
---|---|---|---|---|---|
80n0:17 | Frequency Wait Time | Waiting time [ms] for frequency measurement Once the time specified in the frequency window has elapsed, the system waits for the next positive edge from track A. This enables the update speed for the "Frequency" process data to be optimized, depending on the expected frequencies. At least double the period value of the minimum frequency to be measured should be entered here. t >= 2* (1 / fmin) | UINT16 | RW | 0x53E2 (21474dec) |
80n0:1D | Frequency numerator | Frequency counter value, frequency scaling | UINT32 | RW | 0x00000001 (1dec) |
80n0:1E | Frequency denominator | frequency counter value, used for scaling the frequency and the velocity calculation (increments / unit). | UINT32 | RW | 0x00000001 (1dec) |
80n0:21 | Enable encoder plausibility check | Activation of plausibility check | BOOLEAN | RW | 0x00 (0dec) |
80n0:22 | Enable continuous latch extern | FALSE: The following pulses at the Latch input have no influence on the latch value in index 0x60n0:12 "Latch value" when the bit in index 0x70n0:02 or 0x70n0:04 is set. TRUE: The counter value is written to index 0x60n0:12 "Latch value" at every parameterized edge at the Latch input. | BOOLEAN | RW | 0x00 (0dec) |
80n0:23 | Enable continuous latch extern 2 | FALSE: The following pulses at the Latch extern 2 input have no influence on the latch value in index 0x60n0:22 "Latch value 2" when the bit in index 0x70n0:0C or 0x70n0:0D is set. TRUE: The counter value is written to index 0x60n0:22 "Latch value 2" at every parameterized edge at the Latch extern 2 input. | BOOLEAN | RW | 0x00 (0dec) |
Index 80n1 ENC Settings 1 Ch.n (for n=0 [channel 1], n=1 [channel 2])
Index (hex) | Name | Meaning | Data type | Flags | Default |
---|---|---|---|---|---|
80n1:0 | ENC Settings 1 Ch. (n+1) | Maximum subindex | UINT8 | RO | 0x1D (29dec) |
80n1:17 | Setting the sensor supply 50dec: 5.0 V (default) Refer to the Note on setting the encoder supply | UINT32 | RW | 0x00000032 (50dec) | |
80n1:19 | Filter settings | Filter settings: 10dec: 10 kHz | UINT32 | RW | 0x00001388 (5000dec) |
80n1:1A | Limit counter value | Specifies the value for the upper counter limit. | UINT32 | RW | 0xFFFFFFFF (-1dez) |
80n1:1B | Reset counter value | Specifies the value for the lower counter limit. | UINT32 | RW | 0x00000000 (0dec) |
80n1:1C | Direction inversion hysteresis | Enter the hysteresis in number of increments. A value greater than 0 must be selected. If the counter value exceeds the value, the bit in index 0x60n2:13 "Direction inversion detected" is set in the next PLC cycle. | UINT8 | RW | 0x0A (10dec) |
80n1:1D | Counter mode | 0: Encoder RS422 (diff. input) 2: Encoder TTL (single-ended) 4: Encoder open collector | UINT32 | RW | 0x00000000 (0dec) |