Parameterization as BiSS-C master
Parametrization of the EtherCAT plug-in module EJ5042-0010 as BiSS-C master
- BiSS-C mode (0x80n8:18)
- in the object 0x80n8:18 Mode: BiSS-C (0x00) need to be selected
- CRC polynomial (0x80n8:11)
- The transmission of the data is CRC-secured. The counter polynomial for CRC determination is slave specific.
- Is the CRC transmitted inverted, the 0x80n8:03 “CRC Invert” need to be set to TRUE.
- Clock frequency (0x80n8:13)
- Clock rate, limitations by the max. cable length need to be considered. A runtime compensation for the clock and data line is implemented, therefore the use of long cables and high data rates is possible (max. 10 MHz).
- Multiturn [Bit] (0x80n8:15)
- Number of multiturn bits provided by the slave. If only singleturn bits are provided (e. g. linear encoder) the value can be set to 0.
- Singleturn [Bit] (0x80n8:16)
- Number of singleturn bits provided by the slave.
- Offset LSB Bit [Bit] (0x80n8:17)
- Right aligned offset bits (null bits) can be set, if available (slave specific). The position data is shifted by the number of the offset bits.
 | Note about the counter polynomial The counter polynomial for the CRC determination is manufacturer specific. |
The BiSS-C frame structure is following:
Offset MSB Bit (optional) | Position [max. 64 Bit] | Offset LSB Bit (optional) | Error [1 Bit] | Warning [1 Bit] | CRC [8 Bit] | |
|---|---|---|---|---|---|---|
Not relevant | Multiturn data | Singleturn data | Optional | Status Bits | CRC polynomial | |
0x80n8:15 “Multiturn [Bit]” | 0x80n8:16 “Singleturn [Bit]” | 0x80n8:17 “Offset LSB Bit [Bit]” (right aligned) | 0x80n8:02 | 0x80n8:11 “CRC Polynomial” | ||