KL2502, KL2512 - Dual Channel Pulse Width Output Terminals, 24 V DC

Register overview

 

These registers exist once for each channel

Address
Designation
Default value
R/W
Storage medium
R0
reserved
0x0000 (0dec)
R
 
R1
reserved
0x0000 (0dec)
R
 
Cycle duration
variable
R/W
RAM
Base frequency
variable
R/W
RAM
R4
reserved
0x0000 (0dec)
R
 
PWM raw value
variable
R
RAM
R6
Diagnostic register not used
0x0000 (0dec)
R
 
R7
Command register - reserved
0x0000 (0dec)
R/W
 
Terminal type
0x09C6 (2502dec), 0x09D0 (2512dec)
R
ROM
Software version number
0x????
R
ROM
Multiplex shift register
0x0218 (536dec), 0x0130 (304dec)
R
ROM
Signal channels
0x0218 (536dec)
R
ROM
Minimum data length
0x1818 (6468dec)
R
ROM
Data structure
0x0000 (0dec)
R
ROM
R14
reserved
0x0000 (0dec)
R
 
Alignment register
variable
R/W
RAM
Hardware version number
0x????
R/W
SEEPROM
R17, R18
reserved
0x0000 (0dec)
R/W
SEEPROM
Manufacturer scaling: Offset
0x0000 (0dec)
R/W
SEEPROM
Manufacturer scaling: Gain
0x0100 (256dec)
R/W
SEEPROM
R21…R30
reserved
0x0000 (0dec)
R
SEEPROM
Code word register
variable
R/W
RAM
Feature register
0x0004 (4dec)
R/W
SEEPROM
User offset
0x0000 (0dec)
R/W
SEEPROM
User gain
0x0100 (256dec)
R/W
SEEPROM
Cycle duration PWM
0x0FA0 (4000dec)
R/W
SEEPROM
Duty cycle
0x4000 (16384dec)
R/W
SEEPROM
Pulse duration
0x0005 (5dec)
R/W
SEEPROM
R38…R63
Base frequency 2 (low word)
0x86A0 (34464dec)
R/W
SEEPROM