FB_SimDelayedLatch
Delayed latch
The output 'Q' is delayed with respect to the input 'bIn' by a certain time 'tDelay'. An output 'TRUE'-level for a time 'tLatch' is maintained.
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VAR_INPUT
VAR_INPUT
bEnable : BOOL; (* Activates the Latch *)
bIn : BOOL; (* Input signal *)
tDelay : TIME; (* Delay of the output signal *)
tLatch : TIME; (* Latch time of the delayed output signal
*)END_VAR
bEnable: Activates the block
bIn: Input signal
tDelay: Delay of output signal
tLatch: Latch time of TRUE output level
VAR_OUTPUT
VAR_OUTPUT
Q : BOOL; (* Output signal *)
END_VAR
Q: Output signal
Requirements
Development | Target System | PLC Libraries to include |
|---|---|---|
TwinCAT v2.9.0 Build > 1020 | PC (i386) | TcSimManager.Lib (Standard.Lib; TcBase.Lib; TcSystem.Lib are included automatically) |