Control and status bytes with diagnosis
This description applies to
- KL2751-0000 / KS2751-0000 with firmware versions 3B or higher
- KL2751-0011 / KS2751-0011 with firmware versions 3B or higher
- KL2761-0000 / KS2761-0000
- KL2761-0011 / KS2761-0011
Process data mode
Control byte (for process data mode)
The control byte (CB) is located in the output image, and is transmitted from the controller to the terminal.
Bit | CB1.7 | CB1.6 | CB1.5 | CB1.4 | CB1.3 | CB1.2 | CB1.1 | CB1.0 |
Name | RegAccess | - | - | - | - | - | - | ManualAutoDetect |
Legend
Bit | Name | Description | |
|---|---|---|---|
CB17 | RegAccess | 0bin | Register communication off (process data mode) |
CB1.6 to CB1.1 | - | 0bin | reserved |
CB1.0 | ManualAutoDetect | 1bin | manually start automatic load type detection (rising edge) |
Status byte (for process data mode)
The status byte (SB) is located in the input image, and is transmitted from terminal to the controller.
Bit | SB1.7 | SB1.6 | SB1.5 | SB1.4 | SB1.3 | SB1.2 | SB1.1 | SB1.0 |
Name | RegAccess | Error | Temperature warning | Overload | Operation mode | Synchronous | ||
Legend
Bit | Name | Description | |
|---|---|---|---|
SB1.7 | RegAccess | 0bin | Acknowledgement for process data mode |
SB1.6 | Error | 1bin | A load-side short circuit was detected |
SB1.5 | Temperature warning | 1bin | Overtemperature detected (> 80 °C): the process data are limited to 20 % (the limit is reset automatically when the temperature falls below 60 °C) |
SB1.4 | Overload | 1bin | Overload detected (e.g. when switching higher loads on) |
SB1.3 to SB1.1 | Operation mode | manually set or automatically detected operation mode | |
0dec | automatic load type detection active | ||
1dec | Trailing edge phase control | ||
2dec | Leading edge phase control | ||
3dec | Rectifier mode (positive half-wave with leading edge phase control) | ||
4dec | Rectifier mode (negative half-wave with leading edge phase control) | ||
SB1.0 | Synchronous | 0bin | Terminal is not synchronized with the mains or a short circuit was detected on the load side |
1bin | Terminal has synchronized itself with the mains* | ||
Register communication
Control byte (for register communication)
The control byte (CB) is located in the output image, and is transmitted from the controller to the terminal.
Bit | CB1.7 | CB1.6 | CB1.5 | CB1.4 | CB1.3 | CB1.2 | CB1.1 | CB1.0 |
Name | RegAccess | R/W | Reg. no. | |||||
Legend
Bit | Name | Description | |
|---|---|---|---|
CB1.7 | RegAccess | 1bin | Register communication switched on |
CB1.6 | R/W | 0bin | Read access |
1bin | Write access | ||
CB1.5 to CB1.0 | Reg. no. | Register number: | |
Status byte (for register communication)
The status byte (SB) is located in the input image, and is transmitted from terminal to the controller.
Bit | SB1.7 | SB1.6 | SB1.5 | SB1.4 | SB1.3 | SB1.2 | SB1.1 | SB1.0 |
Name | RegAccess | R/W | Reg. no. | |||||
Legend
Bit | Name | Description | |
|---|---|---|---|
SB1.7 | RegAccess | 1bin | Acknowledgement for register access |
SB1.6 | R | 0bin | Read access |
SB1.5 to SB1.0 | Reg. no. | Number of the register that was read or written. | |