Interrupt

The Interrupts are controlled by the Interrupt function block

Interrupt Controller function block description

• Default FC1121 firmware
  The Sync0 is fixed configured with the pulse length of 100ns and Sync 1 is not available.
• “Sync acknowledge mode” firmware
  Supports Sync0 and Sync1 in acknowledge mode and mapped to the AL Event ESC register. To get this firmware please contact ethercatssc@beckhoff.com.
  NOTE: The AL Event Mask in the ESC register needs to be adapted to support the Sync signals triggering the PDI_ISR. In case of the Beckhoff Slave Stack Code (SSC) this can be done in the function APPL_StartInputHandler. SSC download: www.beckhoff.com/ET9300

Sync0 (slot2) and PDI_ISR (slot1) states are shown in the Interrupt state register (see following table).

Interrupt State Register (0x00) description

To enable the interrupt forward to the PCIe the following settings need to be done.

• Enable interrupt mask for slot1 (PDI_ISR) and slot2 (Sync0) in the interrupt control function block.
• Enable BAR2 register 0x50 bit 7. The interrupt state is shown in BAR2 register 0x40 bit 7.
  In some configurations bit0 has to be set (and the state is also shown in bit0).

Interrupt Mask Register (0x08) description