Control and Status Byte IP/IE60x2

Process data mode

For setting up data exchange (handshake), the control and the status byte are used in process data exchange.

Control Byte

The control byte is transmitted from the controller to the mopdule. It is located in the output image, and can be read or written.

Bit

7

6

5

4

3

2

1

0

Name

RegAccess

OL2

OL1

OL0

-

IR

RA

TR

 

Name

Description

RegAccess

0bin: register communication switched off (Process data mode: Control and status byte in handshake)

OL2-OL1

Count of the data sent

IR

Handshake bit for initialisation of the Bus Terminal/module
If IR is high the Bus Terminal/module performs initialisation. The send and receive functions are blocked, the FIFO pointers are reset and the interface is initialised with the values from the relevant registers (R32-R35, R18). The Bus Terminal/module acknowledges execution of the initialisation with IA.

RA

Handshake bit for receiving data
The Bus Terminal/module notifies the controller via a change of state in RR that the data set defined in IL0-IL1 is located in D0-D4. The data shift is acknowledged in the control byte using RA; only then will new data be transmitted by the Bus Terminal/module to the controller.

TR

Handshake bit for sending data
The handshake for data transmission is provided via this bit. A change of state in TR causes the data set defined via OL0-OL2 (5 bytes maximum) to be loaded into the transmission FIFO buffer. The Bus Terminal/module uses TA to signal execution of this command.

Status byte

The status byte is transmitted from the module to the controller. It is located in the input image, and can only be read.

Bit

7

6

5

4

3

2

1

0

Name

RegAccess

IL2

IL1

IL0

BUF_F

IA

RR

TA

 

Name

Description

RegAccess

0bin: acknowledge for Process data mode (Control and status byte in handshake)

IL2-IL0

Count of the data received

BUF_F

Receive buffer full, any data now received will be lost

IA

Handshake bit for initialisation of the Bus Terminal/module
If IR is high the Bus Terminal/module performs initialisation. The send and receive functions are blocked, the FIFO pointers are reset and the interface is initialised with the values from the relevant registers (R32-R35, R18). The Bus Terminal/module acknowledges execution of the initialisation with IA.

RR

Handshake bit for receiving data
The Bus Terminal/module notifies the controller via a change of state in RR that the data set defined in IL0-IL1 is located in D0-D4. The data shift is acknowledged in the control byte using RA; only then will new data be transmitted by the Bus Terminal/module to the controller.

TA

Handshake bit for sending data
The handshake for data transmission is provided via this bit. A change of state in TR causes the data set defined via OL0-OL2 (5 bytes maximum) to be loaded into the transmission FIFO buffer. The Bus Terminal/module uses TA to signal execution of this command.

Note: When the first data is received there is only one byte in the buffer, because the Bus Terminal/module does not yet know whether other data follows.

Examples

Example of data reception

Note: Evcen in case of the reception of more than 1 byte, there is always the indication for 1 byte in the beginning.

Output
Control byte

Input
Status byte

Description

0000_0000

0xxx_x00x

Start of data transmission

0xxx_000x

0011_x01x

3 bytes in the data bytes are ready to be fetched

0xxx_001x

0011_x01x

Acknowledgement that the data bytes have been fetched

0xxx_001x

0101_x00x

5 bytes in the data bytes are ready to be fetched

0xxx_000x

0101_x00x

Acknowledgement that the data bytes have been fetched

Example of sending data

Output
Control byte

Input
Status byte

Description

0000_0000

0xxx_x0x0

Start of data transmission

0010_00x1

0xxx_x0x0

2 bytes in the data bytes are to be sent

0010_00x1

0xxx_x0x1

2 bytes of data have been loaded into the send FIFO, data is sent

0101_00x0

0xxx_x0x1

5 bytes in the data bytes are to be sent

0101_00x0

0xxx_x0x0

5 bytes of data have been loaded into the send FIFO, data is sent

Example of initialisation

Output
Control byte

Input
Status byte

Description

0xxx_xxxx

0xxx_xxxx

Start of data transmission

0000_0100

0xxx_xxxx

Bus Terminal/module is to be initialised

0000_0100

0000_0100

Bus Terminal/module has completed initialisation

0000_0000

0000_0100

Place Bus Terminal/module once more into data exchange

0000_0000

0000_0000

Bus Terminal/module is ready to operate

Error handling

If a parity, framing or overrun error occurs, the corresponding data is lost in transmission and will not be loaded into the reception FIFO buffer of the Bus Terminal/module.
If the buffer is full, incoming data will be ignored.
The appropriate diagnostic bits in register 6 are set in the event of an error.

 

Register Communication

Serial data cannot be transmitted during register communication.

Control byte

The control byte is only visible if the Fieldbus Box is operated in complete mode. It is located in the output image, and can be read or written.

Bit

7

6

5

4

3

2

1

0

Name

RegAccess

R/W

Register number

 

Name

Description

RegAccess

1bin: Register communication switched on

R/W

0bin: Read
1bin: Write

Register number

Number of the register that is to be read or written.

Status byte

The status byte is only visible if the Fieldbus Box is operating in complete mode. It is located in the input image, and can only be read.

Bit

7

6

5

4

3

2

1

0

Name

RegAccess

R/W

Register number

 

Name

Description

RegAccess

1bin: Acknowledgement for register access

R/W

0bin: Read

Register number

Number of the register that was read or written.