Control and Status Byte IP/IE5109

RegAccess

0_bin: Register communication off (process data mode)

CNT_SET

A rising edge at CNT_SET will set the counter to the value specified in the process data.

EN_LAT_EXT

The external latch input is activated. The value of the counter is entered into the latch register at the first external latch pulse after the EN_LAT_EXT bit becomes valid. When this bit is set, the subsequent pulses do not have any effect on the latch register. It is necessary to ensure that the corresponding latch-valid bit (LAT_EXT_VAL) is cleared by the module before activating the null pulse. This functionality can be set in the feature register (default setting).

RD_PERIOD

The length of the period between two positive edges at input A is measured with a resolution of 200 ns. When the bit is set, this duration is output in data bytes D3 and D4. This functionality can be set in the feature register.

EN_LATC

The null point latch (C input) is activated. The value of the counter is entered into the latch register at the first external latch pulse after the EN_LATC bid becomes valid (it has a higher priority than EN_LAT_EXT). When this bit is set, the subsequent pulses do not have any effect on the latch register. It is necessary to ensure that the corresponding latch-valid bit (LATC_VAL) is cleared by the module before activating the null pulse. (The LATC_VAL bit can only be reset by the module when the C pulse is at a low level.)

RegAccess

0_bin: Acknowledgement for process data mode

STATUS_INPUT

The state of the status input can be represented with this bit. (Can be set via the feature register.)

OVERFLOW

This bit is set if the 16-bit counter overflows (65535 to 0). It is reset when the counter exceeds one third of its measuring range (21845 to 21846) or immediately an underflow occurs.

UNDERFLOW

This bit is set if the 16-bit counter underflows (65535 to 0). It is reset when the counter drops below two thirds of its measuring range (43690 tp 43689) or immediately an overflow occurs.

CNTSET_ACC

The data for setting the counter is accepted from the module.

LAT_EXT_VAL

An external latch pulse has occurred. Data D3 and D4 in the process image corresponds to the current counter value when the bit is set. In order to reactivate the latch input, it is necessary for EN_LAT_EXT first be cleared and then to be set once more.

RD_PERIOD_Q

Data bytes 3 and 4 contain the length of the period.

LATC_VAL

A zero point latch has occurred. Data D3 and D4 in the process image corresponds to the current counter value when the bit is set. In order to reactivate the latch input, it is necessary for EN_LATC first be cleared and then to be set once more.

RegAccess

1_bin: Register communication switched on

R/W

0_bin: Read
1_bin: Write

Register number

Number of the register that is to be read or written.

RegAccess

1_bin: Acknowledgement for register access

R/W

0_bin: Read

Register number

Number of the register that was read or written.