Control and Status Byte IP/IE1502
Process data mode
Control-Byte
The Control byte is always visible in the process image. The byte is located in the output image, and can be read or written.
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Name |
RegAccess |
0 |
CNT_SET |
CNT_INH |
GATE_A |
SET_A |
0 |
EN_A |
|
Name |
Description |
|---|---|
|
RegAccess |
0bin: Register Communication switched off (Process data mode) |
|
CNT_SET |
The module is set to the value specified by the
process data. Setting the counter can be edge or level triggered
(Feature register, bit 2). |
|
CNT_INH |
The counter is stopped as long as this bit is active. The previous counter state is retained. |
|
GATE_A |
State of the Gate-Input is activated in the Status-Byte. (from version D.xxxxxx11) |
|
SET_A |
Set the output |
|
EN_A |
This bit enables the internal functions in register 32. |
Status-Byte
The status byte is always visible in the process image. The status byte is sent from the module to the controller.
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Name |
RegAccess |
0 |
SET_ACC |
INH_ACC |
ST_GATE |
ST_A |
ST_V/R |
0 |
|
Name |
Description |
|---|---|
|
RegAccess |
0bin: Register Communication switched off (Process data mode) |
|
SET_ACC |
The data for setting the counter is accepted from the module. |
|
INH_ACC |
The counter is stopped for as long as this bit is set. |
|
ST_GATE |
The state of the Gate-input is given in this bit, if GATE_A is activated in the Control-Byte. |
|
ST_A |
The state of the output is given in this bit. |
|
ST_V/R |
The state of the up/down input is given in this bit. |
Register Communication
Counter values cannot be transmitted during register communication.
Control Byte
The Control byte is always visible. The byte is located in the output image, and can be read or written.
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Name |
RegAccess |
R/W |
Register number | |||||
|
Name |
description |
|---|---|
|
RegAccess |
1bin: Register Communication switched on |
|
R/W |
0bin: Read |
|
Register number |
Number of the register that is to be read or written |
Status Byte
The status byte is always visible in the process image. The status byte is sent from the module to the controller.
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Name |
RegAccess |
R/W |
Register number | |||||
|
Name |
description |
|---|---|
|
RegAccess |
1bin: Acknowledgement for register access |
|
R/W |
0bin: Read |
|
Register number |
Number of the register that has been read or written |