Configuration for multiple edges per PLC cycle

The timestamp of the last recorded rising or falling signal edge is transferred to the controller once per PLC cycle. If several signal edges occur within a PLC cycle, only the timestamps of one rising and one falling signal edge are transferred.

You can set which timestamp is to be transferred in such a case:

The timestamp of the first detected signal edge in the PLC cycle
The timestamp of the last detected signal edge in the PLC cycle (default)

This setting can be made separately for rising and falling signal edges.

Procedure

The setting is made via one control register per channel:

Channel	Control register
1	0x09A8
2	0x09A9
3	0x09AA
4	0x09AB

To write the desired value to the register, use the FB_EcPhysicalWriteCmd function block from the Tc2_EtherCAT.lib library, for example.

Use bit 0 of the register to configure the detection of rising edges and bit 1 to configure the detection of falling edges:

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
-	-	-	-	-	-	Falling edges	Rising edges

To do this, set the corresponding bit according to the following table:

Bit value	Name	Saved signal edge
0	Continuous (default)	Last signal edge in the PLC cycle
1	Single Event	First signal edge in the PLC cycle

Status byte

The status bytes "Status1" to "Status4" in the process data show what happened in the previous EtherCAT cycle for the respective channel. The meaning of the bits of the status byte depends on the configuration described above:

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
			-	-	Current signal level	Falling edge detected ¹⁾	Rising edge detected ²⁾

¹⁾ Only active if bit 1 is set in the control register.
²⁾ Only active if bit 0 is set in the control register.