Distributed Clocks (DC)
 | EtherCAT System Documentation A basic introduction to the topic of EtherCAT and Distributed Clocks is available in the Download area on the Beckhoff homepage: EtherCAT System Documentation. |
The Box supports the distributed clocks functionality. In order for the Box to provide the current counter reading before the arrival of the querying EtherCAT datagram in the specified process data, a corresponding signal must be generated cyclically in the Box. This signal can be triggered in the Box by two events: the SyncManager (SM) and the distributed clock (DC). Under operation mode selection the following options are available (see Fig. "DC" (Disributed Clocks) tab)
- SM-synchron
The SyncManager event occurs when an EtherCAT frame successfully exchanges process data with the Box. Frame-triggered, the current counter value is thus cyclically determined, but with the low temporal jitter of the Ethernet frame. - DC-synchron
In DC operation mode determination of the counter value is triggered cyclically at constant intervals through the integrated DC unit, synchronous with the bus cycle as standard. More uniform polling offers higher-quality position data for a higher-level control algorithm, for example.
The trigger for the counter reading is the SYNC0 signal.
When DC-Synchron operation mode is activated TwinCAT selects settings that ensure reliable operation of the Box with current position data. This means that determination of the current counter value is triggered by the SYNC0 signal at highly constant intervals and in good time (i.e. with an adequate safety buffer) before retrieving EtherCAT datagram is started.
If necessary, the SYNC0 signal can be shifted along the time axis to the right/later or left/earlier in associated dialogs by specifying a user-defined shift time, see Fig. Advanced Distributed Clock (DC) settings.
- A right-shift (positive shift value) will delay the counter value query, which means the position value becomes more current from the PLC perspective. However, this increases the risk that the position determination may not be finished in time before the arrival of EtherCAT frame, so that no current position value is available in this cycle.
- A left-shift (negative shift value) means the counter value will be queried earlier, resulting in older position values, with an associated increase in the safety buffer before the arrival of the EtherCAT datagram. This setting may be useful in systems with high real-time jitter, if no Industrial PCs from Beckhoff are used for control purposes, for example.
The mentioned notes and information should be used advisedly.
The EtherCAT master automatically allocates SYNC0 and SYNC1 settings that support reliable and timely process data acquisition.
User intervention at this point may lead to undesired behavior.
If these settings are changed in the System Manager, no plausibility checks are carried out on the software side. Correct function cannot be guaranteed for all conceivable setting options.
Default setting
The cyclic reading of the inputs is triggered by the SYNC0 pulse (interrupt) of the DC in the EtherCAT Box. The EtherCAT master sets the Sync Unit Cycle time value to the PLC cycle time and therefore the EtherCAT cycle time as standard. See Fig. Advanced Distributed Clock (DC) settings: 4000 µs = 4 ms, as TwinCAT is in configuration mode.
DC settings
SYNC0
Sync Unit cycle: a multiple of the bus cycle time. The counter value is periodically determined at this interval (in µs).
User defined
Any number up to 232 ns, or about 4.3 seconds. Use of decimal points is allowed.
Shift Time
The Shift Time can be used to shift the SYNC0 pulse for this EtherCAT Box relative to other Boxes/Terminals and the global SYNC pulse in nanosecond steps. If the inputs of several Boxes are read simultaneously, the same value must be entered here.
Based on input reference
If this option is activated an additional Input Shift is added to the configurable terminal-specific SYNC0 shift (user defined). This value is calculated and made available by the EtherCAT master (SysMan/Device EtherCAT/Tab EtherCAT/Advanced Settings/Distributed Clocks/Input Shift Time). As a result, all input terminals in the system (EL1xxx, EL3xxx, EP1xxx, EP3xxx, EPP1xxx, EPP3xxx) read in their inputs as shortly as possible before the EtherCAT frame is fetched, so that controller can be supplied with input data that is as current as possible.
Enable SYNC0
Automatically activated in DC-synchron operation mode.
SYNC1
Additional SYNC pulse, derived from SYNC0 or from the DC itself.
DC settings for EtherCAT master
Higher-level distributed clock parameters can be modified under advanced settings for the EtherCAT master. Refer also to the basic introduction to the topic of EtherCAT and Distributed Clocks; download: the Distributed Clocks system description.
