Parameterization for an SSI encoder
- 1. Select the subordinate device "EP7041-0000" in the Solution Explorer.
- 2. Select the value 1 "SSI" in CoE parameter 8008:18 "Mode".
- The parameter 0x8008:18 "CRC Polynomial" is automatically set to 0. This disables the CRC check because the SSI protocol does not support a checksum.
- The parameter 0x8008:02 "Disable Status Bits" is automatically set to TRUE.
The status bits in "FB Inputs Channel 1 > Status" are not functional. - 3. Configure the encoder with the following CoE parameters:
- 0x8008:13 "Clock Frequency"
Set the clock frequency at which the EP7041-4032 should read the values from the encoder here. Value range: max. 2 MHz.
Select a clock frequency that does not exceed the maximum clock frequency of the encoder.
Also take into account possible restrictions due to long cable lengths. - 0x8008:15 "Multiturn [Bit]"
The multi-turn resolution of the encoder. It corresponds to the number of multi-turn bits transmitted by the encoder.
If the encoder only provides single-turn bits (e.g. linear encoder), set "Multiturn [Bit]" to "0". - 0x8008:16 "Singleturn [Bit]"
The single-turn resolution of the encoder. It corresponds to the number of single-turn bits transmitted by the encoder. - 0x8008:17 „Offset LSB Bits [Bit]“
You can use the "Offset LSB Bits" to hide additional bits that some encoders transmit after the position data in the SSI frame, e.g. a parity bit or a power good bit.
Structure of an SSI frame
Position [max. 64 bits] | Offset LSB Bit | Error [1 bit] | Warning [1 bit] | |
|---|---|---|---|---|
Multi-turn data | Single-turn data | Optional | Status bits, disabled (default) | |
0x80p8:15 | 0x80p8:16 | 0x80p8:17 | 0x80p8:02 | |