Process image

Process image 1:
Fig.8: EP1816-0003 – Process image

DIG Inputs Channel n

 

Process image 2:

Process image 3:

  • Process image 4: Input x
    Digital inputs.
  • Process image 5: Sync error
    This bit is only relevant in "distributed clocks" mode.
    It is TRUE if a synchronization error has occurred in the previous EtherCAT cycle.
  • Process image 6: TxPDO Toggle
    This bit is inverted each time the digital inputs are updated.