Distributed Clock

Oversampling requires a clock generator in the terminal that triggers the individual data sampling events. The local clock in the terminal, referred to as distributed clock, is used for this purpose.
The distributed clock represents a local clock in the EtherCAT slave controller (ESC) with the following characteristics:

In the EL4732 only the lower 32 bits with are realized (~4.2 seconds).

Distributed Clock 1:

EtherCAT and Distributed Clocks

A basic introduction into EtherCAT and distributed clocks is available for download from the Beckhoff website: the “Distributed clocks system description”.

Sample:

The fieldbus/EtherCAT master is operated with a cycle time of 1 ms to match the higher-level PLC cycle time of 1 ms, for example. This means that every 1 ms an EtherCAT frame is sent to the EL4732 for transferring the process data. The local ESC clock therefore triggers an interrupt in the terminal every 1 ms (1 kHz), in order to read the process data provided by the EtherCAT frame. This first interrupt is called SYNC1.

The EL47xx may be set to oversampling n = 10 in the TwinCAT System Manager. This causes the ESC to generate a second interrupt in the terminal with an n-times higher frequency, in this case 10 kHz or 100 µs period. This interrupt is called SYNC0. With each SYNC0 signal the output voltage is transferred to the DAC (digital to analog converter) as a digital value.

Distributed Clock 2:

Voltage output

Both output voltages (channels 1 and 2) are always output simultaneously. This is ensured by the DAC type that is triggered by the SYNC0 pulse. No other operation mode is possible.

Generation of the SYNC0 pulse from the local synchronized clock within the distributed clock network ensures that the analog values are sampled at highly equidistant intervals with the period of the SYNC1 pulse.
The maximum oversampling factor depends on the memory size of the ESC. In the EL47xx it is n = 100.

Distributed Clock 3:

Maximum sampling frequency

A smaller period than 10 µs is not permitted for the EL47xx. The maximum sampling frequency for the EL47xx is therefore 100 kSps (samples per second).
Regarding the calculation of SYNC0 from the SYNC1 pulse based on manual specification of an oversampling factor, please note that for SYNC0 only integer values are calculated at nanosecond intervals.
Sample: 187,500 µs is permitted, 333.3 is not.

Sample:

For SYNC1 = 1 ms oversampling factors such as 1,2,5 or 100 are permitted, but not 3. If implausible values are used the terminal will still reach the OP state but will not output correct process data. This may result in a working counter error.
With 2 channels and n = 100, 2 x 2 x 100 = 400 bytes of process data must be transferred to the EL47xx during each EtherCAT cycle.

Working with DC times in the controller

From the perspective of the controller the distributed clock time has the following characteristics:

The following 3 data types are recommended for handling DC times

Distributed Clock 4:

64- vs. 32-bit representation

Some EtherCAT slaves can only handle 32 bit values for representing the DC time or handle it as a process data. In order to prevent problems caused by overflow (every 4.2 seconds), we strongly recommend using 64-bit times in the controller.

    • 32-bit times supplied to the PLC must be complemented with the current High part
    • In this case only the Low part (lower 32 bit) should be transferred to the hardware

    This sample project

    Distributed Clock 5: (Download) contains a function block that cyclically adds the high part to a 32-bit DC time to make 64 bits.