Example program #2: Parameterization of the CycleCounter and watchdog behavior (from firmware 09)

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Example 2: Parameterization of the CycleCounter and watchdog behavior (from firmware 09)

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In this example the behavior of a EL2262 for the CycleCounter and watchdog case is parameterized with a PLC program and a visualization (from firmware 09).

Data:

• 2 ms cycle time
• 10x oversampling on both channels
• Defined output pattern, which is repeated every 4 cycles

In the System Manager the SyncManager watchdog time is set to 25 ms.

After the PLC has been started the visualization can be used to set the CycleCounter and watchdog behavior for each channel. It is loaded at the push of a button via ADS/acyclic data traffic into the registers 0x0F00/0x0F01 and is then active.

Any PDI errors counted in register 0x030D are read.

For resetting in the event of interruption of the communication the EtherCAT cable to the EL2262 can be unplugged, or the cyclic data transfer can be stopped in the visualization via the DisableEcFrameSending software parameter.

According to the setting from Fig. PLC visualization of the example program, this behavior of the outputs then results:

Using the ESC registers If settings are loaded into ESC registers (in this case 0x0F00, for example), they are retained until they are overwritten or until the system is de-energized. If the system was de-energized, the required values have to be re-loaded into the registers.