Diagnostics

Behavior on error - Watchdog and CycleCounter

The EL2262 output terminal features a parameterizable SM watchdog (SyncManager). In each successful EtherCAT cycle this is 'wound up' again or reset. If it is not used over a certain period, the outputs are set to safe state. This period is 100 ms (default). The EL2262 has no PDI watchdog. For time parameterization of the watchdog in the EL2262 please refer to separate page.

As a further diagnostic tool from the perspective of the terminal the EL2262 features CycleCounter monitoring. The two process data variables CycleCounter0 and CycleCounter1 can be assigned values from the control system on a continuous cyclical basis. Based on the consecutive values the EL2262 can detect whether a frame repetition or a LostFrame has occurred. If the terminal fails to detect an increment +1, the internal register 030D_hex increments by 1. This register can be read acyclically, e.g. by the PLC. See also example program 2.

This enables the EL2262 to respond to two special situations:

no process data communication for a prolonged period --> watchdog reacts
no data received in the current cycle --> CycleCounter monitoring in the EL2262

The following example illustrates the resulting three phases. General signals (as specified by the PLC) are output on channel 1 + 2 of a EL2262 and observed with an oscilloscope.

Diagnostics 1: — Example: error in EL2262 from FW09

In the event of an interruption of the communication, the time response of the terminal function is characterized by the following three phases, cf. Example of error in EL2262 from FW09:

Phase 1: normal operation: Cyclic process data are sent in time to the EL2262, which outputs the data.
In this example channel 1 and 2 exhibit the same signal behavior, 10 times oversampling, cycle time 2 ms, with recurring pattern

general output = TRUE, 1 sample = FALSE
general output = TRUE, 2 samples = FALSE, in the next cycle then
general output = TRUE, 3 samples = FALSE, in the next cycle then
general output = TRUE, 4 samples = FALSE, then starting again.
The CycleCounter variables are also used. The data come from the example program for watchdog parameterization.

Phase 2: CycleCounter monitoring: The EL2262 receives no new process data, the CycleCounter is no longer used.
This may occur over a prolonged period through interruption of communication, or in the short term (1 cycle) through delayed data delivery.
The watchdog is no longer triggered (since no SyncManager events occur) and starts to count down.
The output behavior can be changed from firmware 09. In this example

channel 1 alternately outputs 0/1 during this phase
channel 2 alternately outputs 0 during this phase

Phase 3, watchdog case: the watchdog has run out after the parameterized time, in this example 25 ms.
The outputs now assume the parameterized or safe state.
The output behavior can be changed from firmware 09. In this example

channel 1 continuously outputs the last sample during this phase
channel 2 outputs 1 during this phase

In this example (Fig. Example of error behavior of EL2262 from FW09) the parameterizable behavior from FW09 is already recognizable:

Firmware	CycleCounter monitoring behavior	Watchdog behavior
< FW09	Register 030D_hex: + 1	Outputs: FALSE
>= FW09	Register 030D_hex: + 1, output behavior as parameterized, see below.	output behavior as parameterized, see below.

The procedure for both monitoring situations is as follows:

CycleCounter monitoring (from firmware 09, cf. the example program)

To use the function, the CycleCounter must be operated from the PLC as follows
Byte 0: 8 bit counter, incremented (+1) in each cycle through the PLC
Byte 1: Control byte

Bit 0 = 0: CycleCounter monitoring disabled
Bit 0 = 1: CycleCounter monitoring activated; the counter is evaluated and CC errors are counted in register 030D_hex + 1.
A counter overflow is detected and not interpreted as an error. If the Counter increment is greater than 1 once and subsequently 1 again, only one PDI error is output, since all the counter values after the event have an increment of 1.

If CycleCounter monitoring is not activated, the EL2262 is unable to detect the non-arrival of data and repeats the data of the last sample until the watchdog has run out.
In this example the watchdog is set to 25 ms.

Diagnostics 2: — Default output behavior if CycleCounter monitoring is deactivated

If CycleCounter monitoring is activated, the default is output = FALSE.

Diagnostics 3: — Default output behavior if CycleCounter monitoring is activated

If special CycleCounter behavior is required, this can be set in the ESC via ADS:

Channel 1: register 0x0F00
Bit 0 = TRUE --> parameterization is activated
Bit 1 to 3: default value for CycleCounter error behavior, see below.
Channel 2: register 0x0F01
Bit 0 = TRUE --> parameterization is activated
Bit 1 to 3: default value for CycleCounter error behavior, see below.

For example, a behavior as in Fig. Example: error behavior of EL2262 from FW09 or Parameterized output behavior (system-specific) can be achieved.

Diagnostics 4: — Parameterized output behavior (system-specific)

Notice: the two byte registers 0x0F00 and 0x0F01 should be written simultaneously as 1 word access.

The default values for the CycleCounter behavior are:

Zero: “000”: logical zero is output
ONE: “001”: logical one is output
HOLD: “010”: The value of the last bit from the previous cycle is output
CONTINUE: “011”: A PDI error is output, although the data currently in the buffer are output. These may be outdated data.
ALT: “100”: Zero and one is output alternately
OFF: “101”: The output stage is set to high resistance. No signal level is driven.

	Using the ESC registers If settings are loaded into ESC registers (in this case 0x0F00, for example), they are retained until they are overwritten or until the system is de-energized. If the system was de-energized, the required values have to be re-loaded into the registers.

Watchdog monitoring (from firmware 09, cf. the example program)

If special watchdog behavior is required, this can be set in the ESC via ADS:

Channel 1: register 0x0F00

Bit 0 = TRUE --> parameterization is activated
Bit 4 to 6: default value for watchdog, see below

Channel 2: register 0x0F01

Bit 0 = TRUE --> parameterization is activated
Bit 4 to 6: default value for watchdog, see below

The default behavior for watchdog monitoring is output=FALSE

Notice: the two byte registers 0x0F00 and 0x0F01 should be written simultaneously as 1 word access.

The default values for the watchdog behavior are:

Zero: “000”: logical zero is output
ONE: “001”: logical one is output
HOLD: “010”: The value of the last bit from the previous cycle is output
REP: “011”: The data from the last cycle are output repeatedly
ALT: “100”: Zero and one is output alternately
OFF: “101”: The output stage is set to high resistance. No signal level is driven.

	Using the ESC registers If settings are loaded into ESC registers (in this case 0x0F00, for example), they are retained until they are overwritten or until the system is de-energized. If the system was de-energized, the required values have to be re-loaded into the registers.