Control and status word

Process data mode

Control word (in process data mode)

The control word (CW) is located in the output process image, and is transmitted from the controller to the terminal.

Bit

CW.15

CW.14

CW.13

CW.12

CW.11

CW.10

CW.9

CW.8

CW.7

CW.6

CW.5

CW.4

CW.3

CW.2

CW.1

CW.0

Name

OL7

OL6

OL5

OL4

OL3

OL2

OL1

OL0

Reg

-

-

-

-

IR

RA

TR

Key

Bit

Name

Description

CW.15 ... CW.8

OL7 ... OL0
(OutLenght)

1dec... 22dec

Number of output bytes () available for transfer from the controller to the terminal.

CW.7

Reg (RegAccess)

0bin

Register communication off (process data mode)

CW.6 ... CW.3

-

0bin

reserved

CW.2

IR
(InitRequest)

0bin

The controller once again requests the terminal to prepare for serial data exchange.

1bin

The controller requests terminal for initialization. The transmission and reception functions are disabled, the FIFO pointers are reset and the interface is initialized with the values in the appropriate registers. The terminal acknowledges completion of the initialization via bit SW.2 (IA).

CW.1

RA
(ReceiveAccepted)

toggle

The controller acknowledges receipt of data by changing the state of this bit. Only then new data can be transferred from the terminal to the controller.

CW.0

TR
(TransmitRequest)

toggle

Via a change of state of this bit the controller notifies the terminal that the DataOut bytes contain the number of bytes indicated via the OL bits. The terminal acknowledges receipt of the data in the status byte via a change of state of bit SW.0 (TA). Only now new data can be transferred from the controller to the terminal.

Status word (in process data mode)

The status word (SW) is located in the input process image, and is transmitted from terminal to the controller.

Bit

SW.15

SW.14

SW.13

SW.12

SW.11

SW.10

SW.9

SW.8

SW.7

SW.6

SW.5

SW.4

SW.3

SW.2

SW.1

SW.0

Name

IL7

IL6

IL5

IL4

IL3

IL2

IL1

IL0

Reg

-

-

-

BUF_F

IA

RR

TA

Key

Bit

Name

Description

SW.15 ... SW8

IL7 ... IL0
(InLength)

1dec ... 22dec

Number of input bytes available for transfer from the terminal to the controller.

SW.7

Reg (RegAccess)

0bin

Acknowledgment for process data mode

SW.6 ... SW.4

-

0

reserved

SW.3

BUF_F

1bin

The reception FIFO is full. All further incoming data will be lost!

SW.2

IA
(InitAccepted bit)

1bin

Initialization was completed by the terminal.

0bin

The terminal is ready again for serial data exchange.

SW.1

RR
(ReceiveRequest)

toggle

Via a change of state of this bit the terminal notifies the controller that the DataIn bytes contain the number of bytes indicated via the IL bits. The controller has to acknowledge receipt of the data in the control byte via a change of state of bit CW.1 (RA). Only then new data can be transferred from the terminal to the controller.

SW.0

TA
(TransmitAccepted)

toggle

The terminal acknowledges receipt of data by changing the state of this bit. Only then new data can be transferred from the terminal to the controller

Register communication

Control word (in register communication)

The control word (CW) is located in the output process image, and is transmitted from the controller to the terminal.

Bit

CW.15

CW.14

CW.13

CW.12

CW.11

CW.10

CW.9

CW.8

CW.7

CW.6

CW.5

CW.4

CW.3

CW.2

CW.1

CW.0

Name

RegData:

Reg

R/W

Reg. no.

Key

Bit

Name

Description

CW.15 ... CW.8

RegData:

One byte of data to be written to the register. The other byte is transferred in the adjacent process data byte.

CW.7

Reg

1bin

Register communication switched on

CW.6

R/W

0bin

Read access

1bin

Write access

CW.5 to CW.0

Reg. no.

Register number:
Enter the number of the register that you want to
- read with the input data word DataIN and the HighByte of the status bytes (RegData) or
- write the output data word DataOUT and the HighByte of control word (RegData).

Status byte (for register communication)

The status word (SW) is located in the input process image, and is transmitted from terminal to the controller.

Bit

SW.15

SW.14

SW.13

SW.12

SW.11

SW.10

SW.9

SW.8

SW.7

SW.6

SW.5

SW.4

SW.3

SW.2

SW.1

SW.0

Name

RegData:

Reg

R/W

Reg. no.

Key

Bit

Name

Description

SW.15 ... SW.8

RegData:

One byte of the data read from the register. The other byte is transferred in the adjacent process data byte.

SW.7

RegAccess

1bin

Acknowledgment for register access

SW.6

R

0bin

Read access

SW.5 to SW.0

Reg. no.

Number of the register that was read or written.