Process data exchange
Control byte for process data exchange
The control byte is transferred from the controller to the terminal. It can be used
- in register mode (RegAcc = 1) or
- in process data exchange (RegAcc = 0).
Various actions are triggered in the KL5111 with the control byte:
Bit | CB.7 | CB.6 | CB.5 | CB.4 | CB.3 | CB.2 | CB.1 | CB.0 |
Name | RegAcc | - | - | - | - | Cnt_Set | RD period | EN_Latch |
Bit | Name | Function |
|---|---|---|
CB.7 | RegAcc = 0 | Process data exchange |
CB.6 | - | reserved |
… | … | … |
CB.3 | - | reserved |
CB.2 | Cnt_Set | A rising edge at Cnt_Set will set the counter to the value specified in the process data. |
CB.1 | RD period | If CB.1 is set and bit R32.8 in the feature register is not set: The period duration between two positive edges of input A is measured with a resolution of 200 ns and output in the data bytes DataIN2, DataIN3 and DataIN4. |
CB.0 | EN_Latch | The zero point latch (C input) is activated. At the first external latch pulse after validity of the En_Latch bit, the counter value is stored in the latch register (has priority over En_LatchX). The following pulses have no influence on the latch register when the bit is set (not used when the V/R mode is active, i.e. bit 15 is set in the feature register). |
Status byte for process data exchange
The status byte is transferred from the terminal to the controller. The status byte contains various status bits of the KL5111.
Note: The signal bits A, B, C are output in data byte D2 (bits 3, 4, 5).
Bit | SB.7 | SB.6 | SB.5 | SB.4 | SB.3 | SB.2 | SB.1 | SB.0 |
Name | RegAcc | - | - | Overflow | Underflow | CntSet_Acc | RD_Period_Q | Latch_Val |
Bit | Name | Function |
|---|---|---|
SB.7 | RegAcc = 0 | Acknowledgement for process data exchange |
SB.6 | - | reserved |
SB.5 | - | reserved |
SB.4 | Overflow | This bit is set if an overflow (65535 to 0) of the 16-bit counter occurs. It is reset when the counter exceeds a third of the measuring range (21845 to 21846) or as soon as an underflow occurs. |
SB.3 | Underflow | This bit is set if an underflow (0 to 65535) of the 16-bit counter occurs. It is reset when the counter drops below two thirds of the measuring range (from 43690 to 43689), or immediately an overflow occurs. |
SB.2 | CntSet_Acc | The data for setting the counter has been accepted by the terminal. |
SB.1 | RD_Period_Q | If bit R32.8 in the feature register is not set: If bit R32.8 is set in the feature register: |
SB.0 | Latch_Val | A zero point latch has occurred. The data DataIN3, DataIN 4 in the process image correspond to the latched value with bit set if the period duration was not requested. To reactivate the latch input, En_Latch must first be reset, wait for the acknowledgement of the reset and then set the bit again (not used if V/R mode is active, i.e. bit 15 is set in the feature register). |
or if bit 0 is set in the feature register:
Bit | SB.7 | SB.6 | SB.5 | SB.4 | SB.3 | SB.2 | SB.1 | SB.0 |
Name | RegAcc | - | A-signal | B-signal | C-signal | CntSet_Acc | RD_Period_Q | Latch_Val |
Bit | Name | Function |
|---|---|---|
SB.7 | RegAcc = 0 | Acknowledgement for process data exchange |
SB.6 | - | reserved |
SB.5 | A-signal | State of input A |
SB.4 | B-signal | State of input B |
SB.3 | C-signal | State of input C |
SB.2 | CntSet_Acc | The data for setting the counter has been accepted by the terminal |
SB.1 | RD_Period_Q | If bit R32.8 in the feature register is not set: If bit R32.8 is set in the feature register: |
SB.0 | Latch_Val | A zero point latch has occurred. The data DataIN3, DataIN 4 in the process image correspond to the latched value with bit set if the period duration was not requested. In order to reactivate the latch input, En_Latch must first be reset, wait for the acknowledgement of the reset and then set the bit again. (not used when V/R mode is active i.e. bit 15 set in feature register) |